This invention generally relates to electronic systems and in particular it relates to a switched capacitor scheme for offset compensated comparators.
For pipelined analog-to-digital converter (ADC) designs, offset compensated comparators are often used in the pipeline stages. This is especially true for multi-bit ADCs where the comparator offset needs to be tightly controlled. The usual scheme is to connect these comparators to the driving (previous stage) amplifier through series switches. These switches are opened periodically to isolate the comparators. During this time the comparator inputs are shorted and the offset cancellation phase takes place. If the pre-amplifier in the comparator is configured in unity gain feedback, the offset is stored in the series capacitors connected at the input of the pre-amplifier. This is called input offset correction. If the inputs of the pre-amplifier are shorted, the offset is stored in the series capacitors connected at the output of the pre-amplifier in the comparator. This is called output offset correction.
A typical prior art offset compensated comparator 20 connected to a driving (previous stage) amplifier 22 through series switches 24 and 25 is shown in FIG. 1. The offset compensated comparator 20 includes switches 24-29; comparator preamplifier 30; capacitors 32 and 34; parasitic capacitances 36 and 38; latch 40; inputs VINP and VINM; reference voltages VREFP and VREFM; latched bit 42; and latch enable 44. The previous stage amplifier 22 includes switches 50-60; amplifier 62; and capacitors 64-67.
For the prior art scheme shown in FIG. 1, the voltage at the input of pre-amplifier 30 is given by:                                           V                          Pre              -              INP                                -                      V                          Pre              -              INM                                      =                                            C              S                                                      C                S                            +                              C                P                                              ⁡                      [                                          (                                                      V                    INP                                    -                                      V                    INM                                                  )                            -                              (                                                      V                    REFP                                    -                                      V                    REFM                                                  )                                      ]                                              Eq        .                  xe2x80x83                ⁢        1            
Where Vpre-INP is the voltage at node N1; VPre-INM is the voltage at node N2; CS is the capacitance of capacitors 32 and 34; and CP is the parasitic capacitances 36 and 38 at the input of preamplifier 30. The input to the latch 40 is the input of preamplifier 30 multiplied by the gain of preamplifier 30. Assuming that the offset of preamplifier 30 is completely removed by this scheme, the overall offset of the comparator 20 is then   OFFSET  =            OFFSET      LATCH                      GAIN                  Pre          -          Amp                    xc3x97                        C          S                                      C            S                    +                      C            P                              
Where OFFSETLATCH is the offset of latch 40, and GAINPre-amp is the gain of preamplifier 30.
The series switches 24 and 25 load the driving amplifier 22 and slow it down. For very high speed ADCs ( greater than 40 MSPS), this effect is fairly pronounced. Each of the switches 24 and 25 IS typically a CMOS switch that can be modeled as an R-C load having resistance RSW and Parasitic capacitances CP1 and CP2, as shown in FIG. 2. Also the series resistance RSW of the switches 24 and cause an additional delay from the output of the driving amplifier 22 to the sampling capacitors 32 and 34. This results in an additional offset in the comparator due to incomplete settling of the voltage waveforms across these sampling capacitors.
To decrease the loading effect, the switch resistance RSW cannot be reduced arbitrarily by increasing the switch size as this also increases the parasitic capacitances CP1 and CP2 at he drain and source nodes. Another option is to boost the gate drive of the switch, but this adds to the implementation complexity in the design of high speed ADCs.
An offset compensated comparator has capacitors coupled directly between the inputs of a preamplifier and the outputs of a previous stage amplifier. The comparator also includes additional capacitors coupled between the inputs of the preamplifier and reference voltage nodes. Switches are coupled between the additional capacitors and the reference voltage nodes. An additional switch is coupled between the additional capacitors. In this configuration, there are no series sampling switches between the previous stage amplifier and the comparator. Eliminating the series switches reduces the load seen by the previous stage amplifier, which allows the previous stage amplifier to have a faster settling time. This allows the current in the previous stage amplifier to be decreased which reduces the power consumption.